Article Summary Name Institution Code Compression for Low Power Embedded System Design Introduction The introduction of new Very-large-scale integration (VLSI) technologies and state-of-the art techniques of designing such as the System-on-a-Chip (SOC) has made the creation of multi-million gate chips a reality. The use of SOC has become prevalent in devices with low power consumption such as digital cameras personal digital assistants (PDAs) and cellular phones. System designers understand that the amount of power available for these devices remains fixed. As such it must be budgeted for very wisely if the battery life of these devices is to be prolonged. System designers for this reason consider power reduction to be a major design goal. They have attempted to come up with a number of approaches aimed at reducing energy consumption starting from the physical level up to the system level. A high-level method is likely to have better outcomes percent energy is saved in both the adjusted and un-adjusted cases. Conclusion The approach used in this paper to reduce power consumption focuses on the entire system. These include the CPU the caches main memory the data buses as well as the address bus. Results show that there is a reduction of power consumption of between 18 percent and 82 percent when there is code compression compared to situations where the same was not done. It is worth noting that power reduction was recorded in all the system parts. The performance of the system was maintained and even improved even after a large proportion of power consumption was reduced. The overall chip area is also reduced significantly in the new design. Reference Lekatsas H. Henkel J. & Wolf W. (2000 June). Code compression for low power embedded system design. In Proceedings of the 37th Annual Design Automation Conference (pp. 294-299). ACM. [...]
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