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Bistable Flip-Flop Experiment

Keywords: Bistable Flip-Flop, Standard SR NAND Flip-Flop, RST Flip-Flop

Objectives:

  • To research the properties and performance of cross-coupled inverting logic gates.
  • To create the gates to be able to obtain an experience, in the same time able to understand the Bistable Flip-Flop.

These circuits have been mainly replaced turn into a easy and effective design. These designs for applications including large dimension digital circuits. Although these circuits have been modified, they still have important use range, and it is necessary to understand their characteristics. This test state evidently that digital circuits remain be made from analogue parts. It offers analogue functions correlative to current, voltages and time-varying diversification.

Materials and Equipment:

  • Built-in socket connector bread board
  • A selection of IC devices
  • Jumper cables and connector leads
  • Digital multimeter with test probes

Theory:

Flip-Flop

A standard Bistable circuit is made by simple combo of NAND gates or NOR gates. Hence, produce the mandatory sequential circuit.

Common Sequential Logic circuits:

  1. Clock Influenced- Synchronized to a clock indication.
  2. Event Influenced- Asynchronous. Changing point out when an external event happens.
  3. Pulse Influenced- Combination of Synchronous and Asynchronous.

SR NAND Flip-Flop

This system assembled of two inputs and two outputs. R and S inputs are representing Reset and Place. Q and are represent as outputs of the circuit. Firstly, user need to create the inputs Establish and Reset to a pair of cross combined 2-suggestions 7400 NAND gates in order to shape into a SR Bistable. Thus, the action of reviews may occur from each end result to 1 of the other inputs.

RST Flip-Flop

The device connected and synchronized to a clock indication. The outputs are just trigger when Place (S), Reset (R), and Result in (T) inputs are in logic 1 level. There will we un-trigger when the inputs are in logic 0 level.

NAND gate

  • M74HC00 is a higher rate CMOS QUAD 2-insight NAND gate. Silicon gate C2 MOS technology is applied.
  • The inner circuit is build-up by 3 stages including buffer productivity, which can prevent high noises and produce stable output.

Task Dialogue:

Investigation of an Bistable Flip-Flop

Theoretical Details:

The consequential circuit has two stable situations, when the immediate opinions cross-coupling is implemented among inverting NAND logic gates. Bistable is either of which can be choose by submission of the right insight situation.

R and S inputs are representing Reset and Place. Q and are represent as outputs of the circuit. At standard going, both NAND inputs must normally be logic 1 level. The logic degree of the Q and outputs will become relative.

To stabilizing the two possible expresses, changing the R source temporarily to logic 0 level, that will generate a productivity with logic 1 level. In once, the output result with logic 1 level will be employed to the S type (2nd input), which is logic 1 level. Thus, the Q result will temporarily become a logic 0 level.

While both R and S inputs become logic 0 level at the same period, it is forbidden. With this condition, both Q and outputs will become logic 1 level. Hence, that will override the load-back motion. The final express of the latch will not be resolved before time.

One functional unfavorable of the RS Flip-Flop results from the data that the outputs can change status when either or both of the logic degree of inputs is change. Procedure is non-simultaneous.

Modifying the Bistable Flip-Flop: Creating an RST Flip-Flop

Theoretical Details:

It is similar in the RS NAND Flip-Flop procedure. The R and S inputs are in logic 1 level. The third input (Cause) has been added. The Q and outputs can only change states as the Trigger input reaches logic 1 level. If logic level of Trigger suggestions is 0, the R and S inputs are no result for the outputs.

In a valid operation, the R or S inputs must be logic 1 level, and the Result in suggestions must be logic 1 level and then logic 0 level. In the end, the selected suggestions must be came back to logic 0 level.

Investigation of your NAND gate

Theoretical Details:

The NAND gate is an electronic gate, obtains voltages and currents at its inputs. While connect to the adjustable voltage resource, these may require any value in a real circuit. For instance, since during an insight changes, the output voltages may requires a non-zero time for the change that occurs, therefore the voltages will not be accurately appear to 5V or 0V on a regular basis.

Objective:

To concern the transforms and voltage levels of the result of the NAND gate to the areas of the inputs.

Procedure:

  1. Circuit shown in Physique 2. 7 is produced and an external adjustable voltage from a power supply can be used. Any value from 1k? to 10k? can be taken by R1.
  2. A fixed digital voltage (0 or 5 volts) is put on one terminal of a NAND gate. A changing voltage is put on another terminal.
  3. Firstly, the source voltage Vin is assorted up to a maximum of +5V and Vin against Vout is plotted. Thus, the logic 1 result voltage (V1) and the logic 0 insight voltage (Vgo) are identified.
  4. The outcome unchanging for huge ranges of insight voltage is known.
  5. To found the entire behavior, the harsh initial test is do.
  6. More reading is used.

Conclusion:

All of the objectives are achieved. In this particular test we understand the idea of Bistable Flip-Flop, Standard SR NAND Flip-Flop and RST Flip-Flop. All the properties and performance of cross-coupled inverting logic gates have been analyzed. Experience is obtained during the structure of the gates.

In final result, at standard working of SR NAND Flip-Flop, both NAND inputs must normally be logic 1 level. Thus, the logic level of the Q and outputs can be relative.

While both R and S inputs become logic 0 level at the same period, it is forbidden. In this particular state, both Q and outputs can be logic 1 level. Hence, that will override the load-back motion. The final talk about of the latch will never be resolved in front of time.

For the operation of RST Flip-Flop, the Q and outputs can only just change states while the Trigger input reaches logic 1 level. If logic degree of Trigger suggestions is 0, the R and S inputs are no effect for the outputs. Hence, to secure a valid operation the R or S inputs must be logic 1 level, and the Result in type must be logic 1 level and then logic 0 level. In the long run, the selected source must be came back to logic 0 level.

References:

  • http://www. play-hookey. com/digital/rs_nand_latch. html
  • http://www. play-hookey. com/digital/clocked_rs_latch. html
  • http://us. st. com/stonline/literature/pdf/docs/1879. pdf
  • http://www. electronics-tutorials. ws/sequential/seq_1. html
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